An improved low-power high-throughput log-MAP turbo decoder

This paper presents an efficient implementation of a high-throughput low-power turbo decoder. The design of the component decoder has been optimized so as to achieve low power implementation of the turbo decoder. A collisionfree interleaver has been designed for appropriate parallel decoding operations. Performance enhancing techniques such as parallel processing and pipelining have been applied to realize the highly recursive and complex maximum a posteriori probability (MAP) decoder. Area, power and throughput of the proposed decoder architecture compare favorably with those of an architecture which has been recently reported in literature. The designed decoder, which achieves a throughput of 930 Mbps while consuming 265 mW of power, can be considered to be suitable for a number of real time applications.