Dead-time free pixel readout architecture for ATLAS front-end IC

Author

Einsweiler, K. ; Joshi, A. ; Kleinfelder, S. ; Luo, L. ; Marchesini, R. ; Milgrome, O. ; Pengg, F.

Author_Institution

Lawrence Berkeley Nat. Lab., CA, USA

Volume

46

Issue

3

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

166

Lastpage

170

Abstract

A low-power, sparse-scan, readout architecture has been developed for the ATLAS pixel front-end electronics. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address of the hits and associates them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 μ HP process to meet the requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC has been found to provide dead-time-less ambiguity-free readout at 40 MHz data rate

Keywords

CMOS analogue integrated circuits; discriminators; nuclear electronics; preamplifiers; pulse shaping circuits; readout electronics; trigger circuits; 40 MHz; ATLAS front-end IC; ATLAS inner detector; ATLAS pixel front-end electronics; buffer overflow handling; dead-time free pixel readout architecture; dead-time-less ambiguity-free readout; dual discriminator; event building; low-power sparse-scan readout architecture; mixed-mode full custom IC; pixel readout; serial data link; time over threshold information; Bandwidth; Buffer overflow; Buildings; Circuit testing; Cyclotrons; Data mining; Delay; Filtering; Laboratories; Protocols;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.775508

Filename

775508