Title :
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology
Author :
Gangasani, Gautam R. ; Chun-Ming Hsu ; Bulzacchelli, John F. ; Beukema, Troy ; Kelly, Wayne ; Xu, Hui H. ; Freitas, David ; Prati, Andrea ; Gardellini, Daniele ; Reutemann, Robert ; Cervelli, Giovanni ; Hertle, Juergen ; Baecher, Matthew ; Garlett, Jon ;
Author_Institution :
IBM Syst. & Technol. Group (STG), Hopewell Junction, NY, USA
Abstract :
This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10-12 while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm2.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; error statistics; feedforward; integrated circuit design; jitter; low-power electronics; silicon-on-insulator; transceivers; CDR; DFE transceiver; FFE; FFR scheme; SOI CMOS technology; Si; backplane transceiver; bit rate 32 Gbit/s; bit-error rate; clock and data recovery; decision feedback; feed-forward equalization; high-frequency jitter tolerance; on-chip AC-coupling network; passive feed-forward restore scheme; pattern-dependent baseline wander; size 0.7 mm; size 32 nm; supply ripple; token-based power management scheme; transceiver performance; voltage 1 V; Capacitors; Decision feedback equalizers; Gain; Receivers; Resistors; System-on-chip; Transceivers; Low latency CDR; on-chip AC-coupling; serial links; token-based power management;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2014.2340574
