DocumentCode :
1531222
Title :
Continuously live image processor for drift chamber track segment triggering
Author :
Berenyi, A. ; Chen, H.K. ; Dao, K. ; Dow, S.F. ; Gehrig, S.K. ; Gill, M.S. ; Grace, C. ; Jared, R.C. ; Johnson, J.K. ; Karcher, A. ; Kasen, D. ; Kirsten, F.A. ; Kral, J.F. ; LeClerc, C.M. ; Levi, M.E. ; von der Lippe, H. ; Liu, T.H. ; Marks, K.M. ; Meyer,
Author_Institution :
Lawrence Berkeley Lab., CA, USA
Volume :
46
Issue :
3
fYear :
1999
fDate :
6/1/1999 12:00:00 AM
Firstpage :
348
Lastpage :
353
Abstract :
The first portion of the BABAR experiment Level 1 Drift Chamber Trigger pipeline is the Track Segment Finder (TSF). Using a novel method incorporating both occupancy and drift-time information, the TSF system continually searches for segments in the supercells of the full 7104-wire Drift Chamber hit image at 3.7 MHz. The TSF was constructed to operate in a potentially high beam-background environment while achieving high segment-finding efficiency, deadtime-free operation, a spatial resolution of <0.7 mm and a per-segment event time resolution of <70 ns. The TSF system consists of 24 hardware-identical TSF modules. These are the most complex modules in the BABAR trigger. On each module, fully parallel segment finding proceeds in 20 pipeline steps. Each module consists of a 9U algorithm board and a 6U interface board. The 9U printed circuit board has 10 layers and contains 0.9 million gates implemented in 25 FPGAs, which were synthesized from a total of 50,000 lines of VHDL. The boards were designed from the top-down with state-of-the-art CAD tools, which included gate-level board simulation. This methodology enabled production of a flawless board with no intermediate prototypes. It was fully tested with basic test patterns and 105 simulated physics events
Keywords :
drift chambers; field programmable gate arrays; high energy physics instrumentation computing; image processing equipment; nuclear electronics; pipeline processing; printed circuit design; trigger circuits; 0.7 mm; 6U interface board; 70 ns; 9U algorithm board; 9U printed circuit board; BABAR; Drift Chamber Trigger pipeline; FPGA; Track Segment Finder; drift chamber; image processor; parallel segment finding; spatial resolution; time resolution; track segment triggering; Circuit simulation; Circuit synthesis; Design automation; Field programmable gate arrays; Image segmentation; Pipelines; Printed circuits; Production; Spatial resolution; Testing;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.775542
Filename :
775542
Link To Document :
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