• DocumentCode
    1531299
  • Title

    UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2

  • Author

    Pulimeno, A. ; Graziano, Mariagrazia ; Piccinini, G.

  • Author_Institution
    Dipt. di Elettron., Politec. di Torino, Torino, Italy
  • Volume
    20
  • Issue
    7
  • fYear
    2012
  • fDate
    7/1/2012 12:00:00 AM
  • Firstpage
    1341
  • Lastpage
    1346
  • Abstract
    The increased leakage, yield inefficiency, process, power supply, and temperature variations have significant aftereffects on the performance of complex VLSI architectures especially if mapped on ultra deep sub micrometer (UDSM) technologies. In this paper we assess the technology trend based on three industrial technologies (90, 65, and 45 nm) using a state of the art processor as benchmark: The UltraSparc Niagara 2 from SUN Microsystem. We analyze frequency, dynamic, and static power and area after synthesis varying power supply voltage and temperature. We then compare these exhaustive analyses of system level performance as a function of technology to ITRS device level estimations. The results suggest that this prediction can be of help when addressing both the technological scaling and the variability scenario of the selected technology. We believe that correctly predicting specific values on performance variations when realistic conditions and technologies are changed could provide a valuable information for the architect. Our analysis advises the designer on the effective applicability of the ITRS trends to system performance, but also pinpoints that a reliable system level prediction should better take into account the design complexity.
  • Keywords
    microprocessor chips; multiprocessing systems; ITRS device level estimation; UDSM trend comparison; UltraSparc Niagara2; complex VLSI architecture; dynamic power; frequency analysis; leakage; power supply voltage; processor; reliable system level prediction; size 45 nm; size 65 nm; size 90 nm; static power; technological scaling; temperature variation; ultradeep submicrometer technology; yield inefficiency; Integrated circuit modeling; Performance evaluation; Power supplies; Predictive models; Timing; Transistors; Very large scale integration; CMOS ultra deep submicrometer (UDSM); ITRS; multiprocessor; operating conditions; technology scaling;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2011.2148183
  • Filename
    5782972