DocumentCode :
1531845
Title :
RP-SYN: synthesis of random pattern testable circuits with test point insertion
Author :
Touba, Nur A. ; McCluskey, Edward J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume :
18
Issue :
8
fYear :
1999
fDate :
8/1/1999 12:00:00 AM
Firstpage :
1202
Lastpage :
1213
Abstract :
An automated logic synthesis procedure, called RP-SYN, is described for synthesizing random pattern testable circuits. RP-SYN takes as an input a two-level description of a circuit and a constraint on the minimum fault detection probability (threshold below which faults are considered random pattern-resistant), and generates a multilevel implementation which satisfies the constraint while minimizing the literal count. RP-SYN identifies random-pattern-resistant faults and eliminates them through testability-driven factoring combined with test point insertion. By moving the task of test point insertion from the back-end into the synthesis process, RP-SYN reduces design time and enables better optimization of the resulting implementation. Results are shown for benchmark circuits which indicate that RP-SYN can generally reduce the random pattern test length by at least an order of magnitude with only a small area overhead
Keywords :
automatic test pattern generation; built-in self test; design for testability; fault simulation; integrated circuit testing; logic CAD; logic testing; BIST; CAD; IC testing; RP-SYN; automated logic synthesis procedure; benchmark circuits; design for testability; fault coverage; logic optimization; minimum fault detection probability constraint; multilevel implementation; multiple-level logic; pseudo-random testing; random pattern testable circuits; random-pattern-resistant faults; reduced design time; test point insertion; testability-driven factoring; two-level description; Automatic testing; Circuit faults; Circuit synthesis; Circuit testing; Design optimization; Electrical fault detection; Fault diagnosis; Logic circuits; Logic testing; Process design;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.775638
Filename :
775638
Link To Document :
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