Frequency synthesis using digital-to-frequency conversion and filtering

A novel topology for frequency synthesis using digital-to-frequency conversion and a filtering technique is presented. The implementation uses a high-order digital sigma-delta modulator to encode a DC value, which is then mapped to a corresponding frequency using a digital-to-frequency conversion algorithm. The output bit-sequence with the sigma-delta encoded frequency is then applied to a high-order phase-locked loop (PLL) behaving as a filter operating on the incoming instantaneous frequency. The theory of the proposed scheme is described and validated with simulation and experiment. A prototype board-level implementation with a sixth-order PLL was constructed and frequencies ranging from 30.5 to 44.5 MHz were experimentally generated with a 25 kHz resolution from a single 100 MHz master clock.