Integrated Capacitor Array Matching Characterization

Author

Posch, Werner ; Seebacher, Ehrenfried

Author_Institution

Dept. of Process & Device Characterization, Austriamicrosystems AG, Unterpremstätten, Austria

Volume

25

Issue

3

fYear

2012

Firstpage

331

Lastpage

338

Abstract

A novel characterization methodology for integrated capacitor array mismatch determination is presented. The circuit allows multiplexed biasing of 20 capacitor units and the selection of a specific array on chip. Information about the spatial matching behavior is provided for an entire poly-Si capacitor array, where the relevant parameters are the standard deviations σ(ΔC_i/C) and the offsets μ(ΔC_i/C) of units i. The circuit design and the measurement strategy are discussed in detail. Furthermore, the measurement reproducibility is determined quantitatively and correlations introduced by the extraction method are investigated. The corresponding test chips were successfully realized in 0.35- and 0.18-μm standard CMOS technologies. Results for the poly-Si capacitor array (0.35-μm technology) are presented in this paper.

Keywords

CMOS integrated circuits; capacitors; integrated circuit design; integrated circuit testing; silicon; CMOS technology; Si; array on chip; characterization methodology; circuit design; integrated capacitor array matching; multiplexed biasing; polysilicon capacitor array; size 0.18 mum; size 0.35 mum; spatial matching; standard deviations; test chips; Arrays; Capacitance; Capacitors; Correlation; Standards; Switches; Voltage measurement; Capacitance array; capacitance matching; capacitance mismatch; design for manufacturability (DFM); floating gate; matching; unit capacitors;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2012.2202791

Filename

6212376