Test Structures for Characterization of Through-Silicon Vias

Author

Stucchi, Michele ; Perry, Daniel ; Katti, Guruprasad ; Dehaene, Wim ; Velenis, Dimitrios

Author_Institution

Interuniv. Micro Electron. Center, Leuven, Belgium

Volume

25

Issue

3

fYear

2012

Firstpage

355

Lastpage

364

Abstract

3-D chip stacking using through-silicon vias (TSVs) requires accurate characterization of the TSV, the thinned silicon, and the stacked dies. This paper proposes a set of test structures specifically designed to address the electrical characterization of TSV in terms of resistance, capacitance, leakage, yield, and their impact on the 2-D interconnects of the stacked dies. Examples of the use of these structures are presented, and the observed electrical behaviors are explained with the support of FIB cross-section images.

Keywords

elemental semiconductors; focused ion beam technology; integrated circuit interconnections; integrated circuit testing; silicon; three-dimensional integrated circuits; 2D interconnects; 3D chip stacking; FIB cross-section images; Si; stacked dies; test structures; thinned silicon; through-silicon vias; Arrays; Capacitance; Capacitance measurement; Insulators; Resistance; Substrates; Through-silicon vias; 3-D stack; SPICE simulations; TSV capacitance; TSV leakage; TSV resistance; TSV yield; electrical measurements; ring oscillator (RO); through-silicon via (TSV);

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2012.2202798

Filename

6212379