Title :
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability
Author :
Hwang, Wei ; Gristede, George Diedrich ; Sanda, Pia ; Wang, Shao Y. ; Heidel, David F.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
8/1/1999 12:00:00 AM
Abstract :
This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22°C with Vdd=2.5 V) and 300 mW. The adder core size is 1.6×0.275 mm2. The process technology used was the 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs
Keywords :
CMOS logic circuits; adders; design for testability; high-speed integrated circuits; integrated circuit design; integrated circuit testing; logic design; logic testing; low-power electronics; parallel processing; 0.25 micron; 0.5 micron; 1.5 ns; 2.5 V; 300 mW; 64 bit; CMOS parallel adder; IBM CMOS5X technology; SPA CAD tool; binary carry-lookahead adder; dynamic circuit checking; dynamic parallel adder architecture; evaluate circuits; fast low-power adder; feedback reset chains; high-frequency microprocessors; multigigahertz microprocessor designs; power dissipation; propagation delay; pulse analyzer; self-resetting CMOS circuits; testability; Adders; Automatic testing; CMOS technology; Circuit testing; Feedback circuits; Microprocessors; Performance analysis; Power dissipation; Propagation delay; Pulse circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
