Title :
Low-power dynamic termination scheme using NMOS diode clamping
Author :
Shin, Dong-Ho ; Lee, Young-Min ; Kim, Kyu-hyoun ; Lee, Kwyro
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
8/1/1999 12:00:00 AM
Abstract :
An NMOS diode clamped termination (NDCT) with NMOS threshold voltage (Vth) of around 0 V is proposed as a dynamic termination for a high-speed/low-power chip-to chip interconnection scheme. Both simulation and experimental results for several benchmark circuits show that, compared with open termination, the magnitudes of both overshoot and undershoot for nanosecond-range input pulses are typically less than ~15% of supply voltage (Vcc=3.3 V) with the same order of magnitude in power saving. Finally, the NDCT is found to be very immune to electrostatic discharge, guaranteeing more than 3000 V for a human body model. Our results demonstrate the potentiality of NDCT as a high-speed interconnection scheme
Keywords :
CMOS integrated circuits; VLSI; electrostatic discharge; high-speed integrated circuits; integrated circuit interconnections; low-power electronics; reference circuits; 3.3 V; 3000 V; ESD immunity; NMOS diode clamping; NMOS threshold voltage; dynamic termination; electrostatic discharge; high-speed chip-to chip interconnection; low-power chip-to chip interconnection; low-power dynamic termination scheme; nanosecond-range input pulses; overshoot; undershoot; Circuit simulation; Clamps; Diodes; Electrostatic discharge; Humans; Immune system; Integrated circuit interconnections; MOS devices; Pulse circuits; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
