Title :
A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current
Author :
Sasaki, Katsuro ; Ishibashi, Koichiro ; Shimohigashi, Katsuhiro ; Yamanaka, Toshiaki ; Moriwake, N. ; Honjo, Shigeru ; Ikeda, Shuji ; Koike, Atsuyoshi ; Meguro, Satoshi ; Minato, Osamu
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
10/1/1990 12:00:00 AM
Abstract :
A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm2 and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm2
Keywords :
CMOS integrated circuits; SRAM chips; 0.2 muA; 0.5 micron; 23 ns; 3 V; 4 Mbit; CMOS SRAM; PMOS cross-coupled cascade sense-amplifier; address access time; current mirror; four-level poly; noise-immune data-latch circuit; polysilicon PMOS load memory cell; power-reduction characteristics; quadruple-array; small standby current; static RAM; two-level metal technology; word-decoder architecture; CMOS technology; Circuit noise; Computer architecture; Current supplies; Decoding; Delay effects; Noise reduction; Portable computers; Random access memory; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
