A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Author

Konishi, Yasuhiro ; Dosaka, Katsumi ; Komatsu, Takahiro ; Inoue, Yoshinori ; Kumanoya, Masaki ; Tobita, Youichi ; Genjyo, Hideki ; Nagatomo, Masao ; Yoshihara, Tsutomu

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1112

Lastpage

1117

Abstract

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4×32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode

Keywords

CMOS integrated circuits; DRAM chips; 38 ns; 4 Mbit; 44 muA; DRAM; automatic data retention; back-bias-generator current; battery-backup mode; current-reduction; divided array architecture; double-metal CMOS process technology; memory array; multibit test mode; quad-poly; reduced power consumption; refresh current; Application software; Batteries; CMOS process; Circuits; Energy consumption; Large scale integration; Random access memory; Read-write memory; Testing; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62131

Filename

62131