DocumentCode :
1533938
Title :
A simulation study of copper reflow characteristics in vias
Author :
Friedrich, Loran J. ; Dew, Steven K. ; Brett, Michael J. ; Smy, Tom
Author_Institution :
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Volume :
12
Issue :
3
fYear :
1999
fDate :
8/1/1999 12:00:00 AM
Firstpage :
353
Lastpage :
365
Abstract :
The reliable and complete filling of vias and trenches with an appropriate metal is an important process in the fabrication of microelectronic components. Due to its favorable electronic properties and its reliability, copper is a common choice for replacing aluminum as a metallization material. One metallization procedure of interest is the sputter reflow of copper. The sputter reflow process begins with depositing copper via traditional sputter technologies. The films are subsequently made to fill micrometer and submicrometer trenches and vias through surface diffusion enhanced by annealing. This paper studies fundamental considerations such as deposition rates, underlayer material, and transport mechanisms through numerical simulation using the process simulators SIMSPUD and GROFILMS. The simulations are further used to study via filling using Cu reflow and alternative methods including in situ annealing, three-step deposition, and a four-stage deposition-chemical mechanical polishing procedure. Simulation results are presented as depictions of the film on the feature scale. A discussion of the algorithmic solutions to the three-dimensional problems associated with vias is also provided
Keywords :
annealing; chemical mechanical polishing; copper; metallisation; semiconductor process modelling; sputter deposition; surface diffusion; Cu; GROFILMS; SIMSPUD; annealing; chemical-mechanical polishing; copper metallization; microelectronic fabrication; numerical simulation; process simulator; sputter reflow; surface diffusion; three-dimensional algorithm; trench; via; Aluminum; Annealing; Copper; Fabrication; Filling; Inorganic materials; Materials reliability; Metallization; Microelectronics; Numerical simulation;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.778203
Filename :
778203
Link To Document :
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