Design issues for core-based optoelectronic chips: a case study of the WARRP network router

Author

Raksapatcharawong, Mongkol ; Pinkston, Timothy Mark

Author_Institution

Dept. of Electr. Eng., Kasetsart Univ., Bangkok, Thailand

Volume

5

Issue

2

fYear

1999

Firstpage

330

Lastpage

338

Abstract

We review trends in interconnect bandwidth requirements for multiprocessor systems and technologies proposed to meet these requirements. The benefits and costs of core-based optoelectronic chips are discussed using CMOS-SEED implementations of the WARRP network router as a case study. Results indicate that transistor density and on-chip clock rates of optoelectronic core-based designs can be reduced by as much as 40% and 30%, respectively, but aggregate off-chip bandwidth can be increased by as much as an order of magnitude as compared to all-electronic chip designs

Keywords

CMOS integrated circuits; SEEDs; clocks; integrated circuit design; integrated optoelectronics; multiprocessor interconnection networks; CMOS-SEED implementations; WARRP network router; aggregate off-chip bandwidth; all-electronic chip designs; core-based optoelectronic chips; multiprocessor systems; on-chip clock rates; optical interconnect bandwidth requirements; optoelectronic core-based designs; review; transistor density; Aggregates; Bandwidth; CMOS technology; Chip scale packaging; Clocks; Computer aided software engineering; Integrated circuit technology; Multiprocessing systems; Multiprocessor interconnection networks; Paper technology;

fLanguage

English

Journal_Title

Selected Topics in Quantum Electronics, IEEE Journal of

Publisher

ieee

ISSN

1077-260X

Type

jour

DOI

10.1109/2944.778317

Filename

778317