Title :
Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors-chip design and system implementation
Author :
Kuznia, Charles B. ; Wu, Jen-Ming ; Chen, Chih-Hao ; Hoanca, Bogdan ; Cheng, Lily ; Weber, Allan G. ; Sawchuk, Alexander A.
Author_Institution :
Signal & Image Process. Inst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical nearest-neighbor local interconnections. The smart pixels are implemented using GaAs-GaAlAs multiple-quantum-well diode arrays flip-chip bonded onto complementary metal-oxide-semiconductor circuitry through the Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry. This system provides efficient execution of single-instruction multiple-data algorithms on large data fields and images
Keywords :
cellular logic; flip-chip devices; integrated circuit design; optical arrays; optical interconnections; optical logic; pipeline processing; quantum well lasers; semiconductor laser arrays; smart pixels; 2D parallel pipeline smart pixel array cellular logic processors; Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry; CMOS IC; GaAs-GaAlAs; GaAs-GaAlAs multiple-quantum-well diode arrays; SIMD; SPARCL processing elements; SPARCL processors; cascaded stages; chip design; complementary metal-oxide-semiconductor circuitry; electrical nearest-neighbor local interconnections; flip-chip bonded; free-space digital optic channels; independent optical input/output port; large data fields; optical interconnections; optical logic; optoelectronic parallel pipeline processing system; single-instruction multiple-data algorithms; smart pixel array cellular logic processors; smart pixels; system implementation; two-dimensional array; two-dimensional parallel pipeline smart pixel array cellular logic; Chip scale packaging; Diodes; Integrated circuit interconnections; Logic arrays; Logic design; Optical arrays; Optical interconnections; Pipeline processing; Quantum well devices; Smart pixels;
Journal_Title :
Selected Topics in Quantum Electronics, IEEE Journal of
DOI :
10.1109/2944.778326
