A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

Author

Horiguchi, Masashi ; Aoki, Masakazu ; Etoh, Jun ; Tanaka, Hitoshi ; Ikenaga, Shin´Ichi ; Itoh, Kiyoo ; Kajigaya, Kazuhiko ; Kotani, Hiroaki ; Ohshima, Kazuyoshi ; Matsumoto, Tetsuro

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1129

Lastpage

1135

Abstract

The authors present two developments for a CMOS-DRAM voltage limiter: a precise internal-voltage generator, and a stabilized driver composed of a feedback amplifier with compensation. The voltage limiter´s features include generating a PMOS-V_T difference, being capable of voltage tuning with fuse trimming, and compensation in the driver circuit through zero insertion. It provides a voltage impervious to supply-voltage and substrate-voltage boundings, temperature variation, and process fluctuation, while ensuring the feedback-loop stability with a phase margin of 55° for a time-dependent load of DRAM circuit. The proposed circuits are experimentally evaluated through their implementation in a 16-Mb CMOS DRAM. A temperature dependency of 1.4 mV/°C and a voltage deviation within ±10% for process fluctuation are achieved. The voltage is stabilized within ±3% for V_CC bounce and ±10% for memory operation

Keywords

CMOS integrated circuits; DRAM chips; amplifiers; driver circuits; feedback; limiters; reference circuits; signal generators; stability; tuning; 16 Mbit; compensation; feedback-loop stability; fuse trimming; internal-voltage generator; memory operation; stabilized driver; stabilized feedback amplifier; tunable CMOS-DRAM; voltage limiter; voltage tuning; zero insertion; Circuit optimization; Circuit stability; Driver circuits; Feedback amplifiers; Fluctuations; Fuses; Random access memory; Temperature; Tunable circuits and devices; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62133

Filename

62133