Low-area edge sampler using the Chinese remainder theorem

We present a method of reducing the area of edge sampling circuits that employ the matched delay technique. The method uses the Chinese remainder theorem to decompose a long delay line of length L into n small and separate lines operating in parallel and having a total length proportional to n ⁿ√L. The area reduction is important because it allows lower power dissipation. It also yields higher measurement resolution because delay element variation along the line, which is a function of chip area, is reduced. We also present the design of an ASIC, called the CRT Sampler, using a 2 μm, double metal, single poly CMOS process. We show its layout and give its performance results. We discuss several important design issues, including delay element implementation, maximum measurable delay, output encoding and turn-off delay effects