Title :
A 16-ns 1-Mb CMOS EPROM
Author :
Kuriyama, Masao ; Atsumi, Shigeru ; Imamiya, Ken-ichi ; Iyama, Yumiko ; Matsukawa, Naohiro ; Araki, Hitoshi ; Narita, Kazuhito ; Masuda, Kazunori ; Tanaka, Sumio
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
10/1/1990 12:00:00 AM
Abstract :
A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm2
Keywords :
CMOS integrated circuits; EPROM; 1 Mbit; 100 mus; 16 ns; 425 mW; CMOS EPROM; access time; address transition detection; bit-line bias circuit; data-latch circuit; differential sensing scheme; double-metal process; double-word-line structure; high-speed circuit technology; programming time; threshold monitoring program; threshold voltage shift; word-line delay; CMOS process; CMOS technology; Circuit noise; Decoding; Delay; EPROM; Microprocessors; Monitoring; Semiconductor device noise; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
