An efficient and flexible architecture for high-density gate arrays

The authors describe an efficient and flexible HDGA (high-density gate array) architecture (or sea of transistors) with cells containing three common-gate wide and small transistors on which both logic and memory functions can be relatively densely mapped. The use of titanium-silicide straps for local interconnect (as an alternative to the third metal layer) is evaluated through different designs. The design and performance of an experimental chip in 0.8-μm CMOS technology are discussed. In a comparison of many different standard-cell and common-gate HDGA designs, the HDGA implementations showed equal performance at comparable or even smaller chip areas