A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains

This brief presents a design-for-debug technique for a system-on-a-chip with multiple clock domains. We describe the debugging limitations that can exist between different clock domains when performing a scan-based debug methodology and then propose a scan cell and debug control logic to address those limitations. The proposed scan cell is designed to hold and shift the current or the previous state and support online debug. The debug control logic optimizes a core test infrastructure such as the IEEE 1500 test wrapper to minimize area overhead.