Title :
Stress-Induced Via Voiding in a 130-nm CMOS Imager Process
Author :
Al Qweider, Omar ; Grisanti, Fabio ; Nascetti, Augusto ; Russo, Felice ; Sena, Massimo ; Irrera, Fernanda
Author_Institution :
Dept. of Electron. Eng., Univ. of Rome "La Sapienza", Rome, Italy
fDate :
3/1/2010 12:00:00 AM
Abstract :
This paper provides a detailed and systematic analysis of the mechanisms inducing voiding during high-temperature reliability tests in aluminum via holes in a 130-nm process for CMOS imagers. Finite-element simulations have been performed to derive the mechanical-stress profile in the examined structures, while a set of physical measurements and microscopy techniques have been used to analyze the microstructure of the polycrystalline materials that fill the via holes. Experiments have been designed on the basis of the simulation results, and consisted of some simple changes to the fabrication-technology steps. The failure rate on a few hundreds of samples was checked and compared with reference samples of the production line. The test allowed suggesting variations to a few process parameters that proved to be effective.
Keywords :
CMOS image sensors; crystal microstructure; finite element analysis; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; stress effects; voids (solid); CMOS imager process; aluminum via holes; fabrication technology; failure rate; finite-element simulations; high-temperature reliability tests; mechanical-stress profile; microscopy techniques; physical measurements; polycrystalline materials microstructure; reliability tests; size 130 nm; stress-induced via voiding; Crystal growth; finite-element methods; integrated-circuit (IR) reliability; stress;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2009.2035814