A CMOS mainframe processor with 0.5-μm channel length

Author

Schettler, Helmut ; Haug, Werner ; Getzlaff, Klaus J. ; Starke, Cordt W. ; Bhattacharyya, Arup

Author_Institution

IBM Lab., Boeblingen, West Germany

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1166

Lastpage

1177

Abstract

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability

Keywords

CMOS integrated circuits; IBM computers; VLSI; built-in self test; integrated circuit testing; logic CAD; logic testing; microprocessor chips; pipeline processing; 0.5 micron; 1 micron; 16 kB; 35 to 50 MHz; CMOS VLSI chips; IBM/370 architecture; automatic design system; built-in self-test; cache chips; ceramic multichip module; fixed-point processor; floating-point processor; four stage pipeline; high test coverage; instruction processor; mainframe processor; parity check; processor chip set; reliability; sea-of-gates technique; standard cell approach; Automatic testing; Built-in self-test; CMOS process; CMOS technology; Ceramics; Frequency; Multichip modules; Packaging; Parity check codes; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62139

Filename

62139