A CMOS RISC CPU designed for sustained high performance on large applications

Author

Lotz, Jonathan ; Miller, Bob ; Delano, Eric ; Lamb, Joel ; Forsyth, Mark ; Hotchkiss, Tom

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1190

Lastpage

1198

Abstract

A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAMs. Key performance features include a 3.5-ns 32-b adder, low skew on-chip clock buffers, and cycling large off-chip caches at the operating frequency. The chip has been fabricated using a 1.0-μm CMOS process that utilizes three-level metal and 480000 transistors on a 14×14-mm die

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; pipeline processing; reduced instruction set computing; 1 micron; 15 ns; 3.5 ns; 32 bit; 60 MHz; 90 MHz; CMOS RISC CPU; adder; asynchronous SRAMs; commercial/technical multiuser applications; multichip system; onchip clock buffers; pipeline design; three-level metal; workstation; CMOS process; Central Processing Unit; Coprocessors; Degradation; FETs; Frequency; Pipelines; Reduced instruction set computing; Registers; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62141

Filename

62141