A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

Author

Miyake, Jiro ; Maeda, Toshinori ; Nishimichi, Yoshito ; Katsura, Joji ; Taniguchi, Takashi ; Yamaguchi, Seiji ; Edamatsu, Hisakazu ; Watari, Shigeru ; Takagi, Yoshiyuki ; Tsuji, Kazuhiko ; Kuninobu, Shigeo ; Cox, Steve ; Duschatko, Douglas ; MacGregor, Do

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1199

Lastpage

1206

Abstract

A 1-million transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit

Keywords

CMOS integrated circuits; VLSI; error correction; microprocessor chips; pipeline processing; reduced instruction set computing; 0.8 micron; 2 kB; 20 MFLOPS; 40 MHz; 40 MIPS; 6 kB; 64 bit; ECC circuit; IEEE-754; RISC microprocessor; SPARC; architecture; bus control unit; double-metal CMOS technology; double-precision floating-point operations; error-correcting code; floating-point unit; four-stage pipeline; integer unit; memory management unit; reduced instruction set computer; scalable processor architecture; self-clocked register file; single precision operations; three-way set-associative physical instruction cache; translation lookaside buffers; two-way set-associative physical data cache; word-line transition detection circuits; CMOS technology; Computer aided instruction; Computer architecture; Error correction codes; Integrated circuit technology; Memory management; Microprocessors; Physics computing; Reduced instruction set computing; Registers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62142

Filename

62142