• DocumentCode
    1535585
  • Title

    Second-generation RISC floating point with multiply-add fused

  • Author

    Hokenek, Erdem ; Montoye, Robert K. ; Cook, Peter W.

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • Volume
    25
  • Issue
    5
  • fYear
    1990
  • fDate
    10/1/1990 12:00:00 AM
  • Firstpage
    1207
  • Lastpage
    1213
  • Abstract
    A 440000-transistor second-generation RISC (reduced instruction set computer) floating-point chip is described. The pipeline latency is only two cycles, and a double-precision result is produced every cycle. System throughput and accuracy are increased by using a floating-point multiply-add-fused unit, which carries out a double-precision accumulate as a two-cycle pipelined execution with only one rounding error. While the cycle time (40 ns) is competitive with other CMOS RISC systems, the floating-point performance stretches to the range of bipolar RISC systems (7.4-13 MFLOPS LINPACK). Leading zero anticipation makes the two-cycle pipeline possible by nearly eliminating the additional postnormalization time, and it allows for reduced overall system latency. Partial decode shifters allow complete time sharing for the multiply and data alignment. Improved design techniques for logarithmic addition and higher order counters for multiplication complete this second-generation RISC floating-point unit design
  • Keywords
    CMOS integrated circuits; microprocessor chips; pipeline processing; reduced instruction set computing; 40 ns; 7.4 to 13 MFLOPS; RISC; double-precision accumulate; double-precision result; floating-point chip; higher order counters; logarithmic addition; multiplication; multiply-add-fused unit; partial decode shifters; pipeline latency; reduced instruction set computer; two-cycle pipelined execution; Adders; Circuits; Costs; Delay; Hardware; Pipelines; Reduced instruction set computing; Roundoff errors; Throughput; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.62143
  • Filename
    62143