DocumentCode
1535622
Title
A novel PMOS SOI polysilicon transistor
Author
Pfiester, James R. ; Hayden, James D. ; Gunderson, Craig D. ; Lin, Jung-Hui ; Kaushik, Vidya
Author_Institution
Motorola Inc., Austin, TX, USA
Volume
11
Issue
8
fYear
1990
Firstpage
349
Lastpage
351
Abstract
An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude.<>
Keywords
MOS integrated circuits; insulated gate field effect transistors; integrated memory circuits; ion implantation; random-access storage; semiconductor-insulator boundaries; PMOS SOI polysilicon transistor; Si:B substrate; gate oxide integrity; gate/channel regions; high-density static random access memory circuit; high-energy boron implant; inverted gate electrode; on/off current ratio; selective oxidation; self aligned source/drain regions; self-aligned thin polysilicon channel regions; short-channel behavior; silicon-on-insulator; Boron; Circuits; Electrodes; Implants; MOS devices; Oxidation; Random access memory; SRAM chips; Silicon on insulator technology; Transistors;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.57930
Filename
57930
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