Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell

In this letter, we demonstrate a one-transistor capacitorless DRAM on standard bulk FinFET, using no additional processing. It is shown that, due to the use of the ground-plane doping and optimization of the READ bias conditions, no special process adjustment is required to obtain wide programming windows and long retention times, even for fin widths down to 20 nm.