DocumentCode :
1536405
Title :
Very low cost testers: Opportunities and challenges
Author :
Bedsole, Jay ; Raina, Rajesh ; Crouch, Andrew ; Abadir, Magdy S.
Volume :
18
Issue :
5
fYear :
2001
Firstpage :
60
Lastpage :
69
Abstract :
Prudent application of design-for-testability guidelines can yield designs that don´t require all the expensive features of traditional automated test equipment. The authors describe how the VLSI design and semiconductor test communities can cooperate to greatly reduce testing costs
Keywords :
VLSI; design for testability; integrated circuit testing; VLSI design; design-for-testability; semiconductor test; testing costs; Automatic testing; Built-in self-test; Clocks; Costs; Design for testability; Memory management; Pins; Semiconductor device manufacture; Semiconductor device testing; Very large scale integration;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.953273
Filename :
953273
Link To Document :
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