2 Gbit/s transimpedance amplifier fabricated by 0.35 μm CMOS technologies

Author

Kuo, Chin-Wei ; Hsiao, Chao-Chih ; Yang, Shih-Cheng ; Chan, Yi-Jen

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Volume

37

Issue

19

fYear

2001

fDate

9/13/2001 12:00:00 AM

Firstpage

1158

Lastpage

1160

Abstract

Integrated CMOS transimpedance (TZ) amplifier circuits have been designed and fabricated based on a home-made BSIM model. A 0.35 μm CMOS technology was used for circuit realisation, and a capacitive-peaking design to improve the bandwidth of the TZ amplifier is proposed and investigated. Using this approach provides an easy way to improve the performance of the TZ amplifier; the measured 3 dB bandwidth is enhanced from 875 MHz to 1.35 GHz. The CMOS TZ amplifier design achieves a 2 Gbit/s data rate

Keywords

CMOS analogue integrated circuits; high-speed integrated circuits; integrated circuit design; integrated optoelectronics; optical communication equipment; preamplifiers; 0.35 μm CMOS technologies; 0.35 mum; 1.35 GHz; 2 Gbit/s; 2 Gbit/s transimpedance amplifier; 3 dB bandwidth; CMOS TZ amplifier design; OEIC; capacitive-peaking design; circuit realisation; home-made BSIM model; integrated CMOS transimpedance amplifier circuits; optical communication; output eye diagram; preamplifier;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20010797

Filename

953320