Abstract :
Process engineers have provided generation after generation of CMOS technologies that somehow continue to fulfill Moore´s Law. Architects have shrewdly exploited this capability with innovative schemes that increase parallelism and pipeline depth, change instruction execution order, and drive more speculative operations. These techniques have improved architectural performance at the expense of power, die size, and complexity. Our panelists shared very polarized opinions on whether these boundary conditions and their trends were sustainable and remained practical or if alternative design paradigms are becoming apparent.
