An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration

Author

Ming, Jun ; Lewis, Stephen H.

Author_Institution

California Univ., Davis, CA, USA

Volume

36

Issue

10

fYear

2001

fDate

10/1/2001 12:00:00 AM

Firstpage

1489

Lastpage

1497

Abstract

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm ² in a single-poly 0.5 μm CMOS technology

Keywords

CMOS integrated circuits; adaptive systems; analogue-digital conversion; calibration; errors; 0.5 micron; 268 mW; 3 V; 8 bit; active background calibration; analog-to-digital converter; interstage gain errors; nonlinearity reduction; peak differential nonlinearity; peak integral nonlinearity; pipelined ADC; signal-to-noise/distortion ratio; single-poly CMOS technology; Analog-digital conversion; CMOS analog integrated circuits; CMOS technology; Calibration; Instruments; Integrated circuit technology; Linearity; Operational amplifiers; Redundancy; Testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.953477

Filename

953477