Title :
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology
Author :
Stasiak, Daniel L. ; Mounes-Toussi, F. ; Storino, Salvatore N.
Author_Institution :
IBM Corp., Rochester, MN, USA
fDate :
10/1/2001 12:00:00 AM
Abstract :
A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits
Keywords :
CMOS logic circuits; adders; microprocessor chips; silicon-on-insulator; 0.18 micron; 1.5 V; 440 ps; 64 bit; 660 MHz; CMOS7S; CMOS8S; adder; bipolar current; dynamic circuit; floating body effect; history effect; microprocessor; noise margin; partially depleted SOI technology; Adders; CMOS technology; Cache memory; Circuit noise; Feeds; History; Logic; Microprocessors; Registers; Silicon on insulator technology;
Journal_Title :
Solid-State Circuits, IEEE Journal of
