DocumentCode
1536924
Title
SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests
Author
Zhang, Q. ; Liou, Juin J. ; McMacken, John R. ; Thomson, J. ; Layman, P.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL, USA
Volume
36
Issue
10
fYear
2001
fDate
10/1/2001 12:00:00 AM
Firstpage
1592
Lastpage
1595
Abstract
This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSLM3v3 model. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the drain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compared
Keywords
MOSFET; SPICE; semiconductor device models; semiconductor device testing; BSLM3v3 model; CMOS submicron technology; HSPICE simulation; MOSFET mismatch; SPICE model; drain current; parametric testing; CMOS technology; Circuit simulation; MOSFET circuits; Predictive models; SPICE; Semiconductor device measurement; Semiconductor device modeling; Semiconductor process modeling; Testing; Threshold voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.953490
Filename
953490
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