Analytic and iterative transit-time models for VLSI MOSFETs in strong inversion

Analytic and iterative transit-time models for both long-and short-channel MOSFETs are developed. The derivation is based on common compact IC drain-current models such as BSIM; thus, the short-channel expressions can account for effects such as velocity saturation, channel-length modulation, drain-induced barrier lowering, and two-dimensional charge sharing. The transit-time models are compared with estimates obtained from two-dimensional numerical simulation in order to see how closely simple analytic expressions will follow the more complicated numerical technique. For the long-channel case, traditional first-order analytic transit-time models show good agreement with the numerical results in the saturation region. At low drain bias, the importance of including gate-dependent surface scattering in the analytic mobility model is illustrated. The short-channel expressions also show good agreement at low to middle drain bias. A nonphysical result present at high electric fields which is due to the mobility expression commonly used in IC compact models to account for velocity saturation is identified. A new iterative transit-time model which avoids this problem is presented