DocumentCode :
1537006
Title :
Statistical skew modeling for general clock distribution networks in presence of process variations
Author :
Jiang, Xiaohong ; Horiguchi, Susumu
Author_Institution :
Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
Volume :
9
Issue :
5
fYear :
2001
Firstpage :
704
Lastpage :
717
Abstract :
Clock skew modeling is important in the performance evaluation and prediction of clock distribution networks. This paper addresses the problem of statistical skew modeling for general clock distribution networks in the presence of process variations. The only available statistical skew model is not suitable for modeling the clock skews of general clock distribution networks in which clock paths are not identical. The old model is also too conservative for estimating the clock skew of a well-balanced clock network that has identical but strongly correlated clock paths (for instance, a well-balanced H-tree). In order to provide a more accurate and more general statistical skew model for general clock distributions, we propose a new approach to estimating the mean values and variances of both clock skews and the maximal clock delay of general clock distribution networks. Based on the new approach, a closed-form model is also obtained for well-balanced H-tree clock distribution networks. The paths delay correlation caused by the overlapped parts of path lengths is considered in the new approach, so the mean values and the variances of both clock skews and the maximal clock delay are accurately estimated for general clock distribution networks. This enables an accurate estimate of yields of both clock skew and maximal clock delay to be made for a general clock distribution network.
Keywords :
VLSI; delay estimation; digital integrated circuits; integrated circuit yield; parameter estimation; statistical analysis; synchronisation; timing; clock distribution networks; closed-form model; maximal clock delay; nonidentical clock paths; performance evaluation; performance prediction; process variations; statistical skew modeling; well-balanced H-tree; well-balanced clock network; Clocks; Delay estimation; Helium; Information science; Intelligent networks; Predictive models; Probability; Timing; Very large scale integration; Yield estimation;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.953503
Filename :
953503
Link To Document :
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