DocumentCode :
1537146
Title :
A Power-Optimal Design Methodology for High-Resolution Low-Bandwidth SC 
Modulators
Author :
Porrazzo, Serena ; Cannillo, Francesco ; Van Hoof, Chris ; Cantatore, Eugenio ; Van Roermund, Arthur H M
Author_Institution :
Electr. Eng. Dept., Eindhoven Univ. of Technol., Eindhoven, Netherlands
Volume :
61
Issue :
11
fYear :
2012
Firstpage :
2896
Lastpage :
2904
Abstract :
In this paper, a methodology for the power-optimal design of high-resolution low-bandwidth switched-capacitor ΔΣ modulators (ΔΣMs) is presented. The most power-efficient ΔΣ architecture is identified among single-loop feedback and feedforward topologies with different loop orders N, oversampling ratios OSR, and quantizer resolutions B. Based on this study, an experimental prototype has been implemented in a 0.18- μm CMOS process. It achieves a signal-to-noise ratio of 95 dB over a signal bandwidth fBW of 10 kHz. The prototype operates with a 1.28-MHz sampling rate and consumes 210 μW from a 1.8-V supply.
Keywords :
CMOS integrated circuits; feedback; feedforward; integrated circuit design; sigma-delta modulation; switched capacitor networks; CMOS process; feedforward topologies; high-resolution low-bandwidth SC ΔΣ modulators; high-resolution low-bandwidth switched-capacitor ΔΣ modulators; oversampling ratios; power-efficient ΔΣ architecture; power-optimal design methodology; single-loop feedback; Analog-digital conversion; Bandwidth; Capacitors; Power demand; Resistors; Sigma delta modulation; Analog-to-Digital Converter (ADC); power optimization; sigma–delta modulator; switched capacitor (SC);
fLanguage :
English
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9456
Type :
jour
DOI :
10.1109/TIM.2012.2200812
Filename :
6215049
Link To Document :
