• DocumentCode
    1537474
  • Title

    Clock tree distribution

  • Author

    Yip, K.

  • Author_Institution
    Waterloo Univ., Ont., Canada
  • Volume
    16
  • Issue
    2
  • fYear
    1997
  • Firstpage
    11
  • Lastpage
    14
  • Abstract
    The semiconductor industry is moving toward submicron and deep submicron (0.5 μm and below) technologies. As the chip size keeps decreasing, the chip capacity keeps increasing. New challenges are appearing on high speed ASIC (Application Specified Integrated Circuit) design. Building a balanced clock tree is now essential for the success of any advanced VLSI (Very Large Scale Integration) design. The interconnect wire delay is as important as the logic gate delay.
  • Keywords
    VLSI; application specific integrated circuits; clocks; integrated circuit design; trees (mathematics); balance clock tree distribution; deep-submicron ASIC design; high-speed VLSI circuit; semiconductor chip; Application specific integrated circuits; Buildings; Clocks; Delay; Electronics industry; High speed integrated circuits; Integrated circuit interconnections; Integrated circuit technology; Very large scale integration; Wire;
  • fLanguage
    English
  • Journal_Title
    Potentials, IEEE
  • Publisher
    ieee
  • ISSN
    0278-6648
  • Type

    jour

  • DOI
    10.1109/45.580442
  • Filename
    580442
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1537474