Title :
Optimum halo structure for sub-0.1 μm CMOSFETs
Author :
Yeh, Wen-Kuan ; Chou, Jih-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Taiwan
fDate :
10/1/2001 12:00:00 AM
Abstract :
Optimized halo structures for sub-0.1 μm CMOSFETs are evaluated. Halo profiling using indium implantation for nMOSFETs is investigated over a wide range of implantation dosages and energies. Performance degradation due to interstitial Si resulting from In-halo implantation can be reduced using thermal annealing at medium temperatures for longer periods of time. Lower-temperature composite liner-oxide/SiN-spacer technology is proposed for pMOSFETs to suppress device performance degradation. Optimized halo structures using indium for nMOSFETs and arsenic for pMOSFETs to obtain high-performance sub-0.1 μm CMOSFETs are proposed
Keywords :
MOSFET; annealing; doping profiles; interstitials; ion implantation; 0.1 micron; CMOSFET; Si:As; Si:In; composite liner-oxide/SiN-spacer technology; dopant profiling; interstitial; ion implantation; n-MOSFET; optimum halo structure; p-MOSFET; thermal annealing; Annealing; CMOS technology; CMOSFETs; Implants; Indium; MOSFETs; Silicon compounds; Space technology; Temperature; Thermal degradation;
Journal_Title :
Electron Devices, IEEE Transactions on
