Title :
Framework for performing rapid evaluation of 3D SoCs
Author :
Diamantopoulos, Dionysios ; Siozios, Kostas ; Soudris, Dimitrios
Author_Institution :
Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece
Abstract :
Integrating more functionality in a smaller form factor with lower power consumption pushes traditional semiconductor technology scaling to its limits. Three-dimensional (3D) chip stacking is touted as the silver bullet technology that can keep Moore´s momentum and fuel the next wave of consumer electronic products. Introduced is a framework that enables rapid evaluation of 3D SoCs with existing physical design tools.
Keywords :
power consumption; semiconductor technology; system-on-chip; 3D SoC; 3D chip stacking; Moore momentum; consumer electronic products; physical design tools; power consumption; rapid evaluation framework; semiconductor technology scaling; silver bullet technology; three-dimensional chip stacking;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2012.1321
