Title :
PCFL3: a low-power, high-speed, single-ended logic family
Author :
Kanan, Riad ; Declercq, Michel J.
Author_Institution :
Electron. Lab., Fed. Inst. of Technol., Lausanne, Switzerland
fDate :
9/1/1999 12:00:00 AM
Abstract :
This paper presents a new low-power, high-speed, single-ended logic family called PCFL3. Its operation is based on a bootstrapping technique, used in NMOS. It is fully compatible with direct coupled field-effect transistor logic (DCFL) and two-phase dynamic FET logic (TDFL). PCFL3 is implemented with a standard enhancement/depletion-mode MESFET process and provides all the standard logic functions (NOT, NOR, NAND). Using enhancement-mode FETs only, PCFL3 benefits from good process variation immunity and good noise margins. Measurement results on a ring oscillator are reported. The current consumption of an inverter is reduced by about 53% compared to the DCFL, and the speed is increased by about 50%
Keywords :
MESFET integrated circuits; field effect logic circuits; gallium arsenide; high-speed integrated circuits; low-power electronics; GaAs; PCFL3; bootstrapping technique; enhancement-mode FETs; enhancement/depletion-mode MESFET process; high-speed logic family; low-power logic family; noise margins; process variation immunity; ring oscillator measurements; single-ended logic family; CMOS technology; Circuit noise; Delay; Digital circuits; FETs; Gallium arsenide; Logic; MESFETs; MOS devices; Power dissipation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
