DocumentCode
1537805
Title
A static RAM chip with on-chip error correction
Author
Chiueh, Tzi-Dar ; Goodman, Rodney M. ; Sayano, Masahiro
Author_Institution
Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA
Volume
25
Issue
5
fYear
1990
fDate
10/1/1990 12:00:00 AM
Firstpage
1290
Lastpage
1294
Abstract
A 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip) is described. The linear sum code (LSC)-based ECCRAM is capable of correcting error at any addressed bit as long as there are no more than two errors in the 17 b (the logical row and column) associated with that addressed bit. Test results show that significantly larger error-recovery capability is present in the ECCRAM chip compared to memory chips without error correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with a 3-μm feature size
Keywords
CMOS integrated circuits; SRAM chips; error correction; 2 kbit; 3 micron; CMOS; SRAM; double-metal scalable CMOS process; error-recovery capability; linear sum code; memory chips; on-chip error correction; static RAM chip; Circuit testing; Computer errors; Electrons; Error correction; Logic; Notice of Violation; Prototypes; Random access memory; Read-write memory; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.62154
Filename
62154
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