DocumentCode
1537811
Title
An improved latching pulse design for dynamic sense amplifiers
Author
Yuan, Jiann S. ; Liou, Juin J.
Author_Institution
Dept. of Electr. Eng., Univ. of Central Florida, Orlando, FL, USA
Volume
25
Issue
5
fYear
1990
fDate
10/1/1990 12:00:00 AM
Firstpage
1294
Lastpage
1299
Abstract
A generalized optimal latching pulse for dynamic sense-amplifier design has been derived. The model equations account for threshold-voltage imbalance bit-line capacitance imbalance, current-gain imbalance, gate capacitance and intra-bit-line capacitive coupling effect, channel-length modulation, source-body effect, and temperature sensitivity in a unified manner. Computer simulations of the analytical equations, including those effects, are presented. The analytical results provide physical insight into sensing speed and the sensitivity of optimized waveforms in terms of process imbalances, device model parameters, and circuit design variables. A design implementation for fast sense-amplifier operation is also presented to demonstrate the utility of the model equations for practical application
Keywords
DRAM chips; MOS integrated circuits; amplifiers; equivalent circuits; flip-flops; MOS flip-flop; channel-length modulation; circuit design variables; current-gain imbalance; device model parameters; dynamic sense amplifiers; gate capacitance; intra-bit-line capacitive coupling effect; latching pulse design; source-body effect; temperature sensitivity; threshold-voltage imbalance bit-line capacitance imbalance; Application software; Capacitance; Circuit testing; Computer errors; Computer simulation; Equations; Error correction; Error correction codes; Pulse amplifiers; Solid state circuits;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.62155
Filename
62155
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