Title :
BIST test pattern generator for delay testing
Author :
Girard, P. ; Landrault, C. ; Moréda, V. ; Pravossoudovitch, S.
Author_Institution :
Lab. d´´Inf. de Robotique et de Microelectron., CNRS, Montpellier, France
fDate :
8/14/1997 12:00:00 AM
Abstract :
To detect delay faults in a digital circuit requires a test sequence applied at the nominal frequency of the circuit. Built-in self-test (BIST) is a technique that provides such testing possibilities at speed, without expensive test equipments. A BIST test pattern generator (TPG) design, targeting the detection of delay faults is proposed
Keywords :
automatic testing; built-in self test; delays; digital integrated circuits; fault location; integrated circuit testing; logic testing; BIST; built-in self-test; delay fault detection; delay testing; digital circuit; test pattern generator;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19970998
