Scalar quantisation using a fast systolic array

A systolic array capable of outperforming a table look-up quantiser is proposed. The design has high throughput, can perform uniform or non-uniform quantisation and is suitable for VLSI or field programmable gate array (FPGA) implementation. In the latter case, the array can be used dynamically to both reduce latency and switch between quantisers without the need to reset look-up tables