• DocumentCode
    1538843
  • Title

    Floating gate memories for pulse-stream neural networks

  • Author

    Buchan, L.W. ; Murray, A.F. ; Reekie, H.M.

  • Author_Institution
    Dept. of Electr. Eng., Edinburgh Univ., UK
  • Volume
    33
  • Issue
    5
  • fYear
    1997
  • fDate
    2/27/1997 12:00:00 AM
  • Firstpage
    397
  • Lastpage
    399
  • Abstract
    Floating gate memory cells fabricated in a standard, low-voltage CMOS process have been evaluated experimentally. A circuit has been proposed which allows target voltages on the floating gate to be established. An application of this circuit is demonstrated in the rapid down-loading of weight sets in a pulse-stream neural network for `chip-in-the-loop´ training
  • Keywords
    CMOS memory circuits; VLSI; analogue processing circuits; cellular arrays; neural chips; chip-in-the-loop training; floating gate memories; low-voltage CMOS process; pulse-stream neural networks; rapid down-loading; target voltages; weight sets;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19970251
  • Filename
    581046
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1538843