Title :
A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array
Author :
Otsuji, Tai-Ichi ; Narumi, Naoaki
Author_Institution :
NTT LSI Lab., Kanagawa, Japan
fDate :
5/1/1991 12:00:00 AM
Abstract :
A 3-ns-range, 8-ps-resolution timing generator LSI has been realized by using Si bipolar gate arrays. By adopting a redundant weighted delay-unit matrix based on a process-insensitive polynomial formulation, ±2-ps linearity error has been attained at input clock rates of up to 700 MHz. Thermal noise and interconnection crosstalk have been quantitatively investigated as critical factors causing timing error. By adopting the results to the circuit and layout design, thermal jitter and systematic timing error due to crosstalk were successfully suppressed to less than 8 and ±5 ps. respectively
Keywords :
bipolar integrated circuits; crosstalk; electron device noise; elemental semiconductors; errors; large scale integration; logic arrays; silicon; timing circuits; 3 ns; 700 MHz; Si bipolar gate array; input clock rates; interconnection crosstalk; layout design; process-insensitive polynomial formulation; redundant weighted delay-unit matrix; thermal jitter; thermal noise; timing error; timing generator LSI; Circuit noise; Clocks; Crosstalk; Delay; Integrated circuit interconnections; Large scale integration; Linearity; Polynomials; Thermal factors; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
