Title :
Micro-RISC architecture for the wireless market
Author :
Gonzales, David Ruimy
Author_Institution :
M.Core Technol Center, Motorola Inc., USA
Abstract :
Low-power, embedded, compiler-friendly processors provide increased functionality in highly integrated wireless handsets. The author focuses here on the low-power features of the M.Core architecture and demonstrates its implementation in a cellular baseband transceiver
Keywords :
parallel architectures; reduced instruction set computing; transceivers; M.Core architecture; cellular baseband transceiver; compiler-friendly processors; highly integrated wireless handsets; micro-RISC architecture; wireless market; Baseband; Computer architecture; Electromagnetic interference; Energy consumption; GSM; Multiaccess communication; Multiplexing; Telephone sets; Time division multiple access; Transceivers;
Journal_Title :
Micro, IEEE
