Title :
An 8-b slice GaAs bus logic LSI for a high-speed parallel processing system
Author :
Kameyama, Atsushi ; Kawakyu, Katsue ; Sasaki, Tadahiro ; Seshita, Toshiki ; Terada, Toshiyuki ; Kitaura, Yoshiaki ; Uchitomi, Naotaka ; Mizoguchi, Takamaro ; Toyoda, Nobuyuki ; Maeda, Akira
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
6/1/1991 12:00:00 AM
Abstract :
An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7×7-mm2 chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8-μm WNx gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s
Keywords :
III-V semiconductors; cellular arrays; field effect integrated circuits; gallium arsenide; integrated logic circuits; large scale integration; multiprocessor interconnection networks; 0.8 micron; 10 ns; 2.56 Gbyte/s; 5.5 W; GaAs; III-V semiconductors; LDD; MESFET process; MIMD; WNx gate; building-cell methodology; bus logic LSI; cycle time operation; data transfer rate; dual-port register file; high-speed parallel processing system; logic gates; multi-address read/write operation; power dissipation; standard-cell approach; Gallium arsenide; Large scale integration; Logic devices; Logic gates; MESFETs; Multiprocessor interconnection networks; Parallel processing; Radio frequency; Registers; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
