An introduction to standard-cell VLSI design: Very large scale integration (VLSI) is becoming an important means of producing electronic circuits at low cost, on tight schedules, and with protection for proprietary designs

The rules and overall methodology governing standard cell very large scale integration (VLSI) design are described. Standard-cell VLSI design represents a growing trend in custom parts and falls in between the implementation of arrays of logic gates and the implementation of full custom designs. The main advantage of standard cells over gate arrays is the savings in area. In contrast to gate arrays, a standard-cell design does not have predefined sites on the silicon wafer for the cells; thus, the area can be minimized by optimizing the layout and routing for the given design. The penalty is the increased turnaround time from design to actual samples. Gate-array wafers are pre-made, and only a few mask levels need to be added to implement the circuit.